module mult (
	A, B, P, rst, clk, vld, move, part, step, tick
);

parameter WIDTH = 4;

input rst, clk;
input [WIDTH-1: 0] A, B;
output reg [2*WIDTH-1: 0] P;
output reg vld;

output reg [WIDTH-1: 0] part;
output reg [2*WIDTH: 0] move;
output reg [$clog2(WIDTH+1)-1: 0] step;
output reg tick;
reg c;

// MBFA is assumed to have independent clock, or simply a combinational
// logic. part will be updated as long as any of inputs changes.
multi_bit_full_adder #(.WIDTH(WIDTH)) mbfa (.A(move[2*WIDTH-1: WIDTH]), .B(B), .S(part), .cout(c));

// reset all intermediate stuff 
always @ (posedge rst) begin
	if (rst) begin
		move <= {1'b0, {WIDTH{1'b0}}, A};
		step <= 0;
		tick <= 0;
		P <= 0;
		vld <= 0;
	end
end

// build a shifting signal tick. When tick is high, shift partial product,
// when tick is low, add up with multiplicand on that bit.

always @ (posedge clk) begin
	if (step < WIDTH) begin
		if (tick) begin
			move <= {1'b0, move[2*WIDTH: 1]};
			step <= step + 1;
		end else if (move[0]) begin
			move[2*WIDTH: WIDTH] <= {c, part}; 
		end

		tick <= ~tick;
		vld <= 0;

	end else begin
		P <= move[2*WIDTH-1: 0];
		vld <= 1;
	end
end

endmodule
